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SY89610L 77.75mhz to 694mhz jitter attenuator and low phase noise frequency synthesizer precision edge is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? te l +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com july 2008 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 general description the SY89610L is a 3.3v, fully differential jitter attenuator and frequency synthesizer that accepts a noise clock between 19.44mhz and 694mhz, depending on i/o frequency selection. the output provides an ultra-low jitter clock frequency between 77.75mhz and 694mhz covering sonet/sdh, gigabit ethernet, fibre channel, sas, sata, and many other communication standards. the output jitter of the SY89610L is typically 1ps rms . it has a 1khz to 10khz programmable loop bandwidth to accommodate different jitter attenuation applications and pll requirements. the auto-tune circuit enables precision frequency calibration. the differential input includes micrel?s unique, 3-pin input termination architecture that interfaces to lvpecl, lvds or cml differential signals, (ac- or dc-coupled) as small as 100mv without any level-shifting or termination resistor networks in the signal path. for ac- coupled input interface applications, an on-board output reference voltage (v ref-ac ) is provided to bias the v t pin. the outputs are compatible with 400mv typical swing into 50 ? loads, with rise/fall times guaranteed to be less than 250ps. the SY89610L operates at 3.3v 10% supply and the output can accommodate 1.8v to 3.3v operation with the dedicated output supply. the part is guaranteed to operate over the full industrial temperature range (?40c to +85c). the SY89610L is part of micrel?s precision edge ? product line. datasheets and support documentation can be found on micrel?s web site at: www.micrel.com . precision edge ? features ? accepts high jitter input clock signal and attenuates it to provide ultra-low jitter and phase noise clock signal at the output ? output frequency range: 77.75mhz ? 694mhz ? input frequency range: 19.44mhz ? 694mhz ? phase noise and jitter performance: ? <2ps rms output jitter gen (12khz-20mhz) ? low phase noise: -80dbc/hz at 1khz offset ? cml compatible output signal ? 3-pin input accepts an ac- or dc-coupled differential input (lvds, lvpecl, and cml) ? unique, auto-tune circuitry enables precision frequency calibration ? internal source termination to minimize round-trip reflections ? programmable loop bandwidth: 1khz-10khz ? output enable/disable function ? only one external component needed for lc vco (a filter capacitor) ? includes loss of lock (lol) output pin ? includes auto-tune circuit for precision frequency calibration ? 1.8v 5% to 3.3v 10% output power supply ? 3.3v 10% power supply operation ? industrial temperature range: ?40c to +85c ? available in 32-pin (5mm x 5mm) qfn package applications covers telecom/datacom/storage standards: ? sonet/sdh ? gbe and 10gbe lan phy (w/fec) ? 1/2/4/8g fibre channel ? high-end routers and switches ? telecom transmission equipment ? high speed optical modules ? long haul transport
micrel, inc. SY89610L july 2008 2 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 functional block diagram
micrel, inc. SY89610L july 2008 3 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 ordering information (1) part number package type operating range package marking lead finish SY89610Lmg qfn-32 industrial SY89610L with pb-free bar-line indicator nipdau pb-free SY89610Lmgtr (2) qfn-32 industrial SY89610L with pb-free bar-line indicator nipdau pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 32-pin qfn
micrel, inc. SY89610L july 2008 4 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 pin description pin number pin name pin function 2 vt input termination center-tap: each side of the differential input pair terminates to vt pin. this pin provides a center-tap to a terminat ion network for maximum interface flexibility. see ?input interface applications? subsection. 3 vref-ac reference output voltage: this output biases to v dd -1.4v. it is used when ac-coupling the inputs (in, /in). connect v ref -ac directly to the v t pin. bypass with 0.01f low esr capacitors to v dd . maximum current source or sink is 0.5ma. see ?input interface applications? subsection. 4, 5 refin, /refin differential input pair: this input pair is t he differential signal input to the device. input accepts ac- or dc-coupled differential signals as small as 100mv (200mv pp ). each pin of this pair internally terminates with 50 ? to the v t pin. see figure 1a. 15 /en single-ended input: this ttl/cmos input di sables and enables the output. it has an internal pull-down and will default to a logic low state if left open. when high, the output is forced into the disable state (q = low and /q = high). the pull-down current is typically 0.5a. 8, 9, 18, 23, 24 gnd, exposed pad ground: these are the ground pins for co re and input stage. exposed pad must be connected to a ground plane that is the same potential as the ground pin. 12, 13 clkout, /clkout cml differential output pair: differential buffer ed output copy of the input signal with very low jitter. the output swing is typically 40 0mv. the output pair is referenced to v ddo . output pair can be terminated 100 ? across or 50 ? to v bias . see ?cml output termination? subsection. 10 gndo ground: this is the ground pin for output stage. gndo and gnd must be connected together on the pcb. 11, 14 vddo cml output driver power pins: vddo enables the output stage to operate from a lower supply voltage than the core synthesizer voltage. these outputs can be powered from 1.8v 5% to 3.3v 10% power supply. for a pplications that only require 3.3v reference output operation, vddo and vdd pins may be connected to a common power supply. connect both vddo pins to same power supply. bypass with 0.1f//0.01f low esr capacitors as close to the v dd pins as possible. 20 reset single-ended input: reset is active on the low-to-high edge of the input pulse. it has an internal pull-down and will default to a logic low state if left open. resetting the part starts an auto-tune sequence to provide output frequency closest to input frequency. calibration setting is lost on power down. the pull-down current is typically 0.5a. 19 lol single-ended output: this lvttl/cmos output asserts high when the pll is out of phase lock. lol is asserted if the pll frequency deviates more than 1000ppm for more than 5ms. this prevents false triggering. t he loss of lock pin can be directly connected to /en. 27, 26 filterp, filtern analog input: these pins provide reference for pll loop filter. connect a low esr capacitor across these pins as close to the de vice as possible, clear from any supply lines or adjacent signal lines. see ?external loop filt er considerations? for loop filter values. loop filter capacitor value depends on i/o frequency selecti on. loop filter capacitor layout should include a quiet ground plane under the loop filter capac itor and loop filter (filtp, filtn) pins. recommend 1206, x5r, 6.3v ceramic type, 30%. see ?pll loop filter capacitor table?. 31 gnda ground: this is an analog ground pin for the pll. connect to ?quiet? ground. it is internally referenced to the vco. gnda and ground must be shorted on the pcb. 25, 28, 29 vdda analog power: connect to ?quiet? 3.3v 10% power supply. these pins are not internally connected and must be short ed on the pcb. vdda internally connects to the vco. bypass with 0.1f//0.01f low esr capacitors as close to the pin as possible 21, 22 bw0, bw1 single-ended input: these lvttl/cmos inputs determine the loop bandwidth of the jitter reducing pll. bwsel0 and bwsel1 will default to a logic high state if left open with a typical pull-up current of 1.3 a. see ?loop bandwidth table.?
micrel, inc. SY89610L july 2008 5 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 pin description pin number pin name pin function 7, 30, 32 frqsel0 frqsel1 frqsel2 single-ended input: these lvttl/cmos inputs program internal pre- and post-dividers to determine the i/o synthesis multiplication factor. each fr qsel has three logic states, high, low, and float. these pins will default to a mid-rail (float) state (vdd/2) if left open. these inputs have a pull-up resistor of 180k ? -to-vdd and a pull-down resistor of 180k ? -to-gnd. see ?i/o frequency table? for more details. 16, 17 nc no connect. solder pins to floating pads. 1, 6 vddc positive power supply: vddc pins are connec ted to core and input stage that connects to a 3.3v 10% power supply. bypass with 0.1uf//0.01uf low esr capacitors as close to the v cc pins as possible. bw1 bw0 nominal loop bandwidth (hz) 0 0 1k 0 1 2k 1 0 5k 1 1 10k table 1. loop bandwidth table
micrel, inc. SY89610L july 2008 6 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 input frequency (mhz) output frequency (mhz) frqsel2 frqsel1 frqsel0 p n m input min. input max. output min. output max. mult. 78 78 0 0 0 1 16 1 77.75 86.75 77.75 86.75 1 78 155 0 0 float 1 8 2 77.75 86.75 155.5 173.5 2 78 311 0 0 1 1 4 4 77.75 86.75 311 347 4 78 622 0 float 0 1 2 8 77.75 86.75 622 694 8 155 155 0 float 1 2 8 2 155.5 173.5 155.5 173.5 1 155 311 0 1 0 2 4 4 155.5 173.5 311 347 2 155 622 0 1 float 2 2 8 155.5 173.5 622 694 4 311 311 float 0 1 4 4 4 311 347 311 347 1 311 622 float float 0 4 2 8 311 347 622 694 2 622 622 float 1 float 8 2 8 622 694 622 694 1 19 78 1 0 0 1 16 4 19.44 21.69 77.75 86.75 4 19 155 1 0 float 1 8 8 19.44 21.69 155.5 173.5 8 19 311 1 0 1 1 4 16 19.44 21.69 311 347 16 19 622 1 float 0 1 2 32 19.44 21.69 622 694 32 table 2. i/o frequency table input frequency = 78mhz, 155mhz, 311mhz, 622mhz bw code 00 01 10 11 bw (khz) 1 2 5 10 cext (uf) 4.7 1 0.22 0.15 input frequency = 19mhz bw code 00 01 10 11 bw (khz) 1 2 5 10 cext (uf) 1 0.33 0.15 0.033 table 3. pll loop filter capacitor tables offset/loop bw 1khz 2khz 5khz 10khz 100hz offset -50 -55 -70 -75 dbc/hz 1khz offset -65 -65 -75 -80 dbc/hz 10khz offset -90 -90 -90 -90 dbc/hz 100khz offset -115 -110 -110 -115 dbc/hz table 4. typical phase noise perfor mance (622mhz input, 622mhz output)
micrel, inc. SY89610L july 2008 7 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v dda,, v dd, v ddo )............. ?0.5v to +4.0v input voltage (v in ) .......................... ?0.5v to v ddc + 0.4v cml output voltage (v out ) .............-0.5v to v ddo + 0.4v cml output current (i out ) continuous.......................................................50ma surge .............................................................100ma current (v t ) source or sink on vt pin .............................100ma input current source or sink current on (ref-in, /ref-in) ..50ma current (v ref ) source or sink current on v ref-ac (2) ..............1.5ma maximum junction te mperature........................... 125c lead temperature (solde ring, 20sec .) .................. 260c storage temperature (t s ) ....................?65c to +150c esd (human body model)....................................2000v operating ratings (3) supply voltage (v dda, v dd ) .................+3.0v to +3.60v output supply voltage (v ddo ) ..........+1.71v to +3.60v ambient temperature (t a ) ..................?40c to +85c package thermal resistance (4) qfn still-air ( ja ) ...........................................35c/w junction-to-board ( jb )...........................20c/w dc electrical characteristics (5) v dd = 3.3v + 10%, gnd = 0v; t a = ?40c to +85c, r l is 100 ? across the output pair, unless otherwise stated. symbol parameter condition min typ max units v dd power supply voltage range 3.0 3.3 3.6 v v ddo output voltage range 1.71 3.6 v i ddt total supply current no load max. v dd , v ddo , v dda max. frequency 85 120 ma r diff_in differential input resistance (ref-in-to-/ref-in) 85 100 115 ? v ih input high voltage (ref-in-to-/ref-in) ref-in, /ref-in 1.2 v cc v v il input low voltage (ref-in, /ref-in) ref-in, /ref-in 0 v ih ?0.1 v v in input voltage swing (ref-in, /ref-in) note 6 0.1 1.7 v v diff_in differential input voltage swing (|ref-in ? /ref-in|) 0.2 v v ref-ac output reference voltage v dd ?1.5 v dd ?1.4 v dd ?1.3 v v t_in voltage from input to v t 1.28 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional ope ration is not implied at conditions other than those deta iled in the operational sections of this data sheet. exposure to absolute maximum ra tings conditions for extended periods may affect device reliability. 2. due to the limited drive capability, use for input of the same package only. 3. the data sheet limits are not guaranteed if t he device is operated beyond the operating ratings. 4. package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the pc b. jb and ja values are determined for a 4-layer board in still-air number, unless otherwise stated. 5. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d. 6. v in (max) is specified when v t is floating.
micrel, inc. SY89610L july 2008 8 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 cml output dc electrical characteristics (7) v dda, v dd =+3.3v 10%, v ddo = +1.71v to 3.6v, gnd and gndo = 0v, r l = 100 ? across the outputs; t a = ?40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v oh output high voltage r l = 50 ? to v ddo v ddo -0.13 v ddo -0.085 v ddo -0.04 v v ol output low voltage r l = 50 ? to v ddo v ddo -0.63 v ddo -0.485 v ddo -0.34 v v out output voltage swing see figure 3a 300 400 500 mv v diff_out differential output voltage swing see figure 3b 600 800 1000 mv r out output source impedance 40 50 60 ? lvttl/cmos dc electri cal characteristics (7) v ddc = 3.3v 10%, gnd = 0v, t a = ?40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.5 v v il input low voltage 0.8 v v oh output high voltage i oh /i ol < 4 ma 2.7 v v ol output low voltage i oh /i ol < 4 ma 0.2 v i ih input high current -1 3 a i il input low current -5 1 a freqsel dc electrical characteristics (7) v ddc = 3.3v 10%, gnd = 0v, t a = ?40c to + 85c, unless otherwise stated. symbol parameter condition min typ max u nit s v ih input high voltage 2.5 v v il input low voltage 0.8 v v oh output high voltage i oh /i ol < 4 ma 2.7 v v ol output low voltage i oh /i ol < 4 ma 0.2 v v im input mid voltage vdd/2 ? 0.1 vdd/2 vdd/2 + 0.1 v i ih input high current 5 50 a i il input low current -50 -5 a notes: 7. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d.
micrel, inc. SY89610L july 2008 9 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics v dda, v ddc =+3.3v 10%, gnd and gndo = 0v, r l = 100 ? across the outputs; input t r /t f < 400ps; t a = ?40c to +85c, unless otherwise stated. symbol parameter condition min typ max units f in input frequency range v in > 100mv clock 19.44 694 mhz f out output frequency range v out > 200mv clock 77.75 694 mhz f vco internal vco frequency 1244 1388 mhz lol maximum i/o frequency pll out of lock, ~4ms sustained i/o difference -1000 1000 ppm i/o frequency = 155mhz 450 ms t lock acquisition lock time (8) max vco frequency 550 ms refin t r, t f input rise/fall times 20% to 80% 400 ps clkout t r, t f output rise/fall times 20% to 80% 110 160 250 ps refin c duty input duty cycle 40 60 % clkout c duty output duty cycle 48 50 52 % bw1 = 0, bw0 = 0 750 1000 1250 hz bw1 = 0, bw0 = 1 1500 2000 2500 hz bw1 = 1, bw0 = 0 3750 5000 6250 hz bw loop bandwidth, locked bw1 = 1, bw0 = 1 7500 10000 12500 hz notes: 8. reset low-to-high to lol high-to-low.
micrel, inc. SY89610L july 2008 10 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 jitter characteristics (9) v dda , v dd =+3.3v 10%, gnd= 0v, r l = 100 ? across the outputs; input t r /t f < 400ps; t a = ?40c to +85c, unless otherwise stated. contact factory for 1khz a nd 2khz loop bandwidth transfer characteristics. bw setting: 1khz, bw1:0 = 00 symbol parameter condition min typ max units 12khz to 20mhz (ideal ref input and supply) 1 2 j gen clkout rms jitter generation 50khz to 80mhz (ideal ref input and supply) 1 2 ps rms j tol jitter tolerance 10 ns f bw jitter transfer bandwidth lbw = 1khz 1000 hz j p jitter peaking <1khz 0.1 db bw setting: 2khz, bw1:0 = 01 symbol parameter condition min typ max units jgen clkout rms jitter generation 12khz to 20mhz (ideal ref input and supply) 1 2 psrms 50khz to 80mhz (ideal ref input and supply) 1 2 jtol jitter tolerance 10 ns fbw jitter transfer bandwidth lbw = 2khz 2000 hz jp jitter peaking <1khz 0.1 db bw setting: 5khz, bw1:0 = 10 symbol parameter condition min typ max units jgen clkout rms jitter generation 12khz to 20mhz (ideal ref input and supply) 1 2 psrms 50khz to 80mhz (ideal ref input and supply) 1 2 jtol jitter tolerance 10 ns fbw jitter transfer bandwidth lbw = 5khz 5000 hz jp jitter peaking <1khz 0.1 db bw setting: 10khz, bw1:0 = 11 symbol parameter condition min typ max units jgen clkout rms jitter generation 12khz to 20mhz (ideal ref input and supply) 1 2 psrms 50khz to 80mhz (ideal ref input and supply) 1 2 jtol jitter tolerance 10 ns fbw jitter transfer bandwidth lbw = 10khz 10,000 hz jp jitter peaking <1khz 0.1 db note: 9. 5k and 10k loop bandwidth settings are recommended due to be tter jitter performance with jitter bandwidth below 12k hz. th e use of 1k and 2k bandwidth settings may be acceptable in certain applications where jitter bandwidth is limited to above 12k hz. please conta ct the factory for additional information.
micrel, inc. SY89610L july 2008 11 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 functional description overall function the SY89610L is designed to accept a high-jitter signal and provide an ultra-low jitter and ultra-low phase noise cml compatible clock signal. unlike normal buffers, the SY89610L is a jitter attenuator since it does not transfer jitter across from input to output. this makes this product an ideal solution for precision clock applications. lc voltage control oscillator (vco) the SY89610L uses an extremely low phase noise vco to prevent jitter at the output. at low frequencies, the pll produces more phase noise. to offset the noise, the lc vco provides an extremely low phase noise signal that feeds to the output circuit. unlike many competitive vcos, this vco only requires a single external component, which is a filter capacitor. external loop filter considerations the SY89610L features an external pll loop filter that allows the user to tailor the plls behavior. it is recommended that ceramic capacitors with nop or x7r dielectric be used because they have very low effective series resistance. all othe r filter components are on- chip. internally, the filter has a resistor in series with the external capacitor and a much smaller capacitor in parallel with the series combination of the internal resistor and external capacitor. the selectable pll bandwidths from 1khz-to-10 khz allows the user to select between different loop filter values. the external capacitor must be placed as close to the device pins as possible. while laying out the board, keep any supply or signal traces lines away from the capacitor. loop filter capacitor layout should include a quiet ground plane under the loop filter capacitor and loop filter pins. power supply filtering techniques as with any high-speed integrated circuit, power supply filtering is very important. at a minimum, vdda, vdd, and all vddo pins should be individually connected using via to the power supply plane, and separate bypass capacitors should be used for each pin. to achieve optimal jitter performance, each power supply pin should use separate instances of the circuit shown in power supply scheme below. power supply scheme jitter generation jitter generation is the amount of jitter generated by the part at the output when there is no jitter present at the input clock. while the vco and pll are sources of jitter in a synthesizer, the different loop bandwidth options aid in reducing jitter. the SY89610L guarantees less than 2ps rms . see jitter characteristics subsection. phase noise the SY89610L has very low phase noise at 1khz offset from the center frequency. phase noise is measured at the output with a jitter-free signal injected at the input. the loop bandwidth settings have a minor impact on the phase noise values. for 10khz loop bandwidth, we guarantee the phase noise less than -80dbc/hz. see phase noise curve.
micrel, inc. SY89610L july 2008 12 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 phase noise characteristics
micrel, inc. SY89610L july 2008 13 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 input and output stage figure 1a. simplified differential input buffer figure 1b. simplified cml output buffer single-ended and di fferential swings figure 2a. single-ended swing figure 2b. differential swing
micrel, inc. SY89610L july 2008 14 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 input interface applications figure 3a. cml interface (dc-coupled) option: may connect v t to v cc figure 3b. cml interface (ac-coupled) figure 3c. lvpecl interface (dc-coupled) figure 3d. lvpecl interface (ac-coupled) figure 3e. lvds interface
micrel, inc. SY89610L july 2008 15 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 cml output termination figure 4a. cml dc-coupled termination figure 4b. cml dc-coupled termination figure 4c. cml ac-coupled termination
micrel, inc. SY89610L july 2008 16 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 package information 32-pin (5mm x 5mm) qfn packages notes: 1. package meets level 2 moisture sensitivity classification. 2. all parts are dry-packed before shipment. 3. exposed pad must be soldered to ground for proper thermal management
micrel, inc. SY89610L july 2008 17 m9999-071008-d hbwhelp@micrel.com or (408) 955-1690 pcb thermal consideration for 32-pin qfn package (always solder, or equivalent, the exposed pad to the pcb) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life support app liances, devices or systems is a purchaser ?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2008 micrel, incorporated.

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